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MF1493-03
S1D15G10D08B000
Rev. 1.0
"Seiko Epson is neither licensed nor authorized to license its customers under one or more patents held by Motif Corporation to use this integrated circuit in the manufacture of liquid crystal display modules. Such license, however, may be obtained directly from MOTIF by writing to: Motif, Inc., c/o In Focus Systems, Inc., 27700A SW Parkway Avenue, Wilsonville, OR 97070-9215, Attention: Vice President Corporate Development." Seiko Epson Corporation 2002, All rights reserved.
Rev. 1.0
Contents
1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. BLOCK DIAGRAM ............................................................................................................................................. 2 4. PIN LAYOUT ..................................................................................................................................................... 3 5. LIST OF DEVICE MODELS ............................................................................................................................... 3 6. PIN COORDINATE ............................................................................................................................................ 4 7. PIN DESCRIPTION ........................................................................................................................................... 7 8. FUNCTIONAL DESCRIPTION ........................................................................................................................ 12 9. COMMANDS ................................................................................................................................................... 30 10. ABSOLUTE MAXIMUM RATING ..................................................................................................................... 42 11. ELECTRIC CHARACTERISTICS .................................................................................................................... 43 12. MPU INTERFACES (EXAMPLES FOR YOUR REFERENCE) ....................................................................... 53 13. PERIPHERAL CONNECTION EXAMPLES .................................................................................................... 58 14. EEPROM INTERFACE .................................................................................................................................... 60 15. CAUTIONS ...................................................................................................................................................... 61
-i-
Rev. 1.0
S1D15G10D08B000
1. DESCRIPTION
S1D15G10 series are the LCD drivers equipped with the liquid crystal drive power circuit to realize color display with one chip. S1D15G10 can be directly connected to the MPU bus to store parallel or serial gray-scale display data from MPU on the built-in RAM and to generate liquid crystal drive signals independent from MPU. S1D15G10 generates 396 segment outputs and 132 common outputs for driving liquid crystal. It incorporates the display RAM with capacity of 396 x 132 x 4 (16 gray-scale). A single dot of pixel on the liquid crystal panel corresponds to 4 bits of the built-in RAM, enabling to display 132 (RGB) x 132 pixels with one chip. Read or write operations from MPU to the display RAM can be performed without resorting to external actuating clock signals. S1D15G10 allows you to run the display system of high performance and handy equipment at the minimum power consumption thanks to its low-power liquid crystal drive power circuit and oscillation circuit.
2. FEATURES
* Number of liquid crystal-drive outputs: 396 segment outputs and 132 common outputs. * Low cross talk by frame rate modulation. * 256 color from 4096-color display or full 4096-color display. When 256 color from 4096-color display is selected: 8 gray-scale for red and green and 4 gray-scale for blue (intermediate tone is selected with the command). When 4096-color display is selected: 16 gray-scale for red, green and blue. * Direct data display with display RAM (When the LCD is set to normally black) RAM bit Data "0000" ... OFF (Black) "1111" ...ON (Maximum RGB display) (Normally black LCD, using "inverse display" command) * Partial display function: You can save power by limiting the display space. This function is most suited for handy equipment in the standby mode. * Display RAM : 396 x 132 x 4 = 209,088 bits. * MPU interface: S1D15G10 can be directly connected to both of the 8/16-bit parallel 80 and 68 series MPU. Two type serial interface are also available. * 3 pins serial : CS, SCL and SI (D/C + 8-bit data) * 4 pins serial : CS, SCL, SI and A0 * Abundant command functions: Area scroll function, automatic page & column increment function, display direction switching function and power circuit control function. * Built-in liquid crystal drive power circuit: S1D15G10 is equipped the charge pump booster circuit, voltage follower circuit and electric volume control circuit. * Oscillation circuit with built-in high precision CR (external clock signals acceptable) * EEPROM interface functions * Supply voltage Power for input/output system power: VDDI-GND=1.7V to 3.6V Power for internal circuit operation: VDD-GND=2.6V to 3.6V Reference power for booster circuit: VDD2-GND=2.6V to 3.6V Power for liquid crystal drive: V3-MV3=12.0V to 21.0V * Wider operational range: -40C to +85C. * Shipping from: Chip with gold bump. COF. * Note that the radiation resistant design or light resistance design in strict sense is not employed for S1D15G10.
Rev. 1.0
EPSON
1
S1D15G10D08B000
3. BLOCK DIAGRAM
COM132 SEG396 COM1 SEG1
********************
********
V3 V2 V1 VC MV1 MV2(GND) MV3 SEG Drivers COM Drivers
CAP1+ CAP1- CAP2+ CAP2- VCLS CAP3+ CAP4+ CAP4- CAP5+ CAP5- SEG decoder Display data latch
COM decoder Shift register
Power circuit
Page address
Display timing signal generation circuit
DDRAM 396 x 132 x 4
Block address
SLP YSCL F1,F2 CA FR SYNC CL DOFF M/S
I/O buffer VR VDD2 Column address
Oscillation circuit
CLS
VDD3 to 5 VDD VDDI GND GND2 to 4 EEPROM interface
Command decoder
Bus holder
MPU interface
WR(R/W)
IF1,IF2,IF3
D15 to D0
CLOCK
RESET
2
EPSON
TEST2
RD(E)
TEST
SDA
RES
SCL
CS
A0
SI
Rev. 1.0
S1D15G10D08B000
4. PIN LAYOUT
734 Die No. 1 Y (0,0) X 190 191
Chip size Chip thickness Die No. Potential on board Bump size
23.58 mm x 2.70 mm 725 m25 m (for reference) See Section 5 "List of Device Models." GND Tolerance: 4 m (reference) Driver output side: (SEG1 to 396) 41.5 m (COM1 to 33, 101 to 132) 48m (COM34 to 100) 45m Driver input side: 82 m x 109 m Bump pitch Driver output side: 42 m I/O signal line side:100 m min. Bump height 22.5 m4 m (for reference) : The tolerance is specified in delivery specification. Alignment coordinate 1 (-11449.8, -454.35) 2 (11424.0, -729.35) Mark size a = 80 m b = 20 m
b a
5. LIST OF DEVICE MODELS
Model name Die No. Frame frequency /built-in oscillation frequency 180 Hz/47.52 kHz
S1D15G10D08B000 D15GAD8B0
Rev. 1.0
EPSON
3
S1D15G10D08B000
6. PIN COORDINATE
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin Name NC NC V3L V3L V3L V3L V2L V2L V2L V1L V1L V1L VCL VCL VCL VCLSL VCLSL VCLSL MV1L MV1L MV1L MV3L MV3L MV3L NC NC NC NC NC TESTA TESTA TESTA TESTA TESTA CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2- CAP2- CAP2- CAP2- CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1- CAP1- CAP1- CAP1- GND2 GND2 GND2 GND2 GND3 X -11607.0 -11487.0 -11367.0 -11247.0 -11127.0 -11007.0 -10887.0 -10767.0 -10647.0 -10527.0 -10407.0 -10287.0 -10167.0 -10047.0 -9927.0 -9807.0 -9687.0 -9567.0 -9447.0 -9327.0 -9207.0 -9087.0 -8967.0 -8847.0 -8714.0 -8614.0 -8514.0 -8414.0 -8314.0 -8169.0 -8054.0 -7939.0 -7824.0 -7709.0 -7589.0 -7474.0 -7359.0 -7244.0 -7129.0 -7009.0 -6889.0 -6769.0 -6649.0 -6529.0 -6414.0 -6299.0 -6184.0 -6069.0 -5949.0 -5829.0 -5709.0 -5589.0 -5446.0 -5341.0 -5236.1 -5131.1 -5026.1 Y -1187.0 Xsize 82 Ysize 109 PAD No. 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Pin Name GND3 GND3 GND GND GND VDD3 VDD3 VDD4 VDD4 TESTB VDD VDD VDDI VDDI VDDI VDDI FR YSCL F1 F2 DOFF CA SYNC SLP SDA RESET CLOCK TEST1 GND *6 VDDI *6 CL CLS GND *6 VDDI *6 MS A0 GND *6 VDDI *6 TEST2 WR GND VDDI D0 D1 D2 D3 D4 D5 D6 D7 GND VDDI D8 D9 D10 D11 D12 X -4921.0 -4816.0 -4711.0 -4606.0 -4501.0 -4396.0 -4291.0 -4186.0 -4081.0 -3976.0 -3871.0 -3766.0 -3661.0 -3556.0 -3451.0 -3346.0 -3235.0 -3081.0 -2927.0 -2773.0 -2619.0 -2465.0 -2311.0 -2157.0 -2003.0 -1849.0 -1695.0 -1541.0 -1387.0 -1287.0 -1187.0 -1033.0 -879.0 -779.0 -679.0 -525.0 -371.0 -271.0 -171.0 -17.0 137.0 237.0 337.0 491.0 645.0 799.0 953.0 1107.0 1261.0 1415.0 1569.0 1669.0 1769.0 1923.0 2077.0 2231.0 2385.0 Y -1187.0 Xsize 82
Unit: m
Ysize 109
72 82
72 82
72 82
72 82
72 82
4
EPSON
Rev. 1.0
S1D15G10D08B000
Unit: m
PAD No. 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Pin Name D13 D14 D15 GND VDDI RD RES GND *6 VDDI *6 IF1 IF2 IF3 GND *6 VDDI *6 SI SCL CS VDDI VDDI GND GND GND GND GND4 GND4 GND4 GND4 VDD VDD VDD5 VDD5 VDD2 VDD2 VDD2 VDD2 CAP4+ CAP4+ CAP4+ CAP4- CAP4- CAP4- CAP5+ CAP5+ CAP5+ CAP5- CAP5- CAP5- MV3R MV3R MV3R TESTC TESTC TESTC TESTD TESTD TESTD MV1R X 2539.0 2693.0 2847.0 3001.0 3101.0 3201.0 3355.0 3509.0 3609.0 3709.0 3863.0 4017.0 4171.0 4271.0 4371.0 4525.0 4679.0 4861.0 4966.0 5071.0 5176.0 5281.0 5386.0 5491.0 5596.0 5701.0 5806.0 5911.0 6016.0 6121.0 6226.0 6372.0 6477.0 6582.0 6687.0 6807.0 6927.0 7047.0 7167.0 7287.0 7407.0 7527.0 7647.0 7767.0 7887.0 8007.0 8127.0 8247.0 8367.0 8487.0 8607.0 8727.0 8847.0 8967.0 9087.0 9207.0 9327.0 Y -1187.0 Xsize 82 Ysize 109 PAD No. 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 to 227 228 229 230 231 232 to 261 262 263 264 265 266 267 268 269 to 660 661 662 663 664 665 666 667 Pin Name MV1R MV1R VR VR VCR VCR VCR V1R V1R V1R V2R V2R V2R V3R V3R V3R V3R NC NC NC NC NC NC NC COM1 COM2 COM3 COM4 COM5 COM6 to COM32 COM33 COM34 COM35 COM36 COM37 to COM66 COM67 COM68 NC NC NC SEG396 SEG395 SEG394 to SEG3 SEG2 SEG1 NC NC NC COM69 COM70 X 9447.0 9567.0 9686.9 9807.0 9927.0 10047.0 10167.0 10287.0 10407.0 10527.0 10647.0 10767.0 10887.0 11007.0 11127.0 11247.0 11367.0 11487.0 11607.0 11661.0 11605.0 11549.0 11493.0 11445.0 11397.0 11349.0 11301.0 11253.0 11205.0 *1 Y -1187.0 Xsize 82 Ysize 109
72 82
72 82
72 82
1175.5
30
137
9861.0 9815.0 9770.0 9725.0 *2
28
8330.0 8285.0 8240.0 8195.0 8152.5 8111.0 8069.5 *3
26
-8240.0 -8281.5 -8325.5 -8371.0 -8416.0 -8461.0 -8506.0
28
Rev. 1.0
EPSON
5
S1D15G10D08B000
Unit: m
PAD No. 668 to 694 695 696 697 698 to 727 Pin Name COM71 to COM97 COM98 COM99 COM100 COM101 to COM130 X *4 Y 1175.5 Xsize 28 Ysize 137 PAD No. 728 729 730 731 732 733 734 Pin Name COM131 COM132 NC NC NC NC NC X -11349.0 -11397.0 -11445.0 -11493.0 -11549.0 -11605.0 -11661.0 Y 1175.5 Xsize 30 Ysize 137
-9766.0 -9813.0 -9861.0 *5
30
*1: You can determine the position on X coordinate from the formula "1157.0-48* (n-201)", where the BUMP No. is "n". *2: You can determine the position on X coordinate from the formula "9680.0-45* (n-232)", where the BUMP No. is "n". *3: You can determine the position on X coordinate from the formula "8028.0-41.5* (n-269)", where the BUMP No. is "n". *4: You can determine the position on X coordinate from the formula "-8551.0-45* (n-668)", where the BUMP No. is "n". *5: You can determine the position on X coordinate from the formula "-9909.0-48* (n-698)", where the BUMP No. is "n". *6: This pin is used to pull up or pull down nearby pins. Thus, it can't be used for feeding power.
6
EPSON
Rev. 1.0
S1D15G10D08B000
7. PIN DESCRIPTION
7.1 Power Supply Pins
Pin name VDDI VDD I/O Input power Power supply Step-up power Description They are used to connect the power for input signals. They are connected to VCC - the system power. When the system power is smaller than 2.6V, they must be connected another 2.6V or greater power supply. They are used to connect the power supply for the primary step-up. The relative magnitude of potential among the pins, namely VDD2VDDVDD1, must be observed. They are power supply pins on the power circuit *1. They are power supply pins on the oscillation circuit *1. They are connected to the system ground. They are grounding pins on the power circuit *2. They are grounding pins on the oscillation circuit *2. These pins are provided on the multi-level power supply for liquid crystal drive. Relative magnitude of potential among the pins, namely V3L(R)V2L(R)V1L(R)VCL(R)MV1L(R)GNDMV3L(R), must be observed. When or the internal power supply is turned on, predetermined voltage is output at respective pins. L and R of each power supply are connected inside the IC. They are provided on the common driver operating power supply. Regulator input pins. Number of pins 14 4
VDD2
6
VDD3,VDD5 Power supply Power VDD4 supply GND Power supply GND2, Power GND4 supply GND3 Power supply Power V3L, V3R V2L, V2R supply V1L, V1R VCL, VCR MV1L, MV1R MV3L, MV3R VCLSL (VOUT) VR Power supply Input power
4 2 15 8 3 38
3 2
*1: Since VDD, VDD3, VDD4 and VDD5 are not internally connected, they must be externally connected to VCC - the system power. *2: Since GND, GND2, GND3 and GND4 are not internally connected, they must be externally connected to the system GND (ground).
Rev. 1.0
EPSON
7
S1D15G10D08B000 7.2 Pins on Liquid Crystal Drive Power Circuit
Pin name CAP1+ CAP1- CAP2+ CAP2- CAP3+ CAP4+ CAP4- CAP5+ CAP5- I/O O O O O -- O O O O Description They connect the positive going side of the primary step-up capacitor. They connect the negative going side of the primary step-up capacitor. They connect the positive going side of the secondary step-up capacitor. They connect the negative going side of the secondary step-up capacitor. They are unused pins. Their pins must be fixed at OPEN. They connect the positive going side of the tertiary step-up capacitor. They connect the negative going side of the tertiary step-up capacitor. They connect the positive going side of the tertiary step-up capacitor. They connect the positive going side of the tertiary step-up capacitor. Number of pins 5 4 5 4 5 3 3 3 3
8
EPSON
Rev. 1.0
S1D15G10D08B000 7.3 MPU Interface Pins
Pin name D15 to D0 I/O I/O Description They connect to the standard 8-bit or 16-bit MPU bus via the 8/16-bit bi-directional bus. When the following interface is selected and the CS pin is high, the following pins become high impedance. 1 8-bit parallel: D15-D18 are in the state of high impedance 2 Serial interface: D15-D0 are in the state of high impedance This pin is used to input serial data when the serial interface is selected. This pin is used to input serial clock when the serial interface is selected. The data is converted in the rising edge. These pins are used to select either of the MPU interfaces. Depending on status of IF1, IF2 and IF3, following selection is made. IF1 HIGH HIGH HIGH LOW LOW LOW A0 I IF2 HIGH HIGH LOW HIGH LOW LOW IF3 HIGH LOW LOW HIGH HIGH LOW MPU interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 9-bit serial 8-bit serial 1 Number of pins 16
SI SCL IF1, IF2 IF3
I I I
1 1 3
CS RD (E)
I I
WR (R/W)
I
RES
I
Normally, the least significant bit of the MPU's address bus is connected to identify a parameter or display data from a command. HIGH: Indicates that data entered to D15 to D0 or SI is a parameter or display data. LOW: Indicates that data entered to D15 to D0 or SI is a command. This function is disabled when the 9-bit serial interface is selected. This pin is used to enter chip select signal. It is activated when CS = LOW, enabling interface with MPU. * It goes active LOW when connected to the 80 series MPU. This pin is used to connect RD signal from the 80 series MPU. The data bus is maintained in the output status as long as this signal is LOW. * It goes active HIGH when connected to the 68 series MPU. In this case, this pin is used to enter the enable clock from 68 series MPU. * It goes active LOW when connected to the 80 series MPU. This pin connects WR signal from the 80 series MPU. Signal on the data bus is latched at the positive going edge of WR signal. * This pin enters the read/write signal when connected to the 68 series MPU. R/W = HIGH: Read R/W = LOW: Write Causing RES to LOW performs initialization. Reset operation is performed according the level of RES signal.
1 1
1
1
Rev. 1.0
EPSON
9
S1D15G10D08B000 7.4 Liquid Crystal Drive Circuit Signals
Pin name M/S CLS I/O I I Description This pin is used to select either the master or slave operation. M/S = HIGH: Master operation It is used to select the display clock. CLS = HIGH: Built-in CR oscillation is used. CLS = LOW: External clock is used. When the external clock is used (CLS = LOW), the signal is entered to CL pin. This pin inputs or outputs the display clock. It outputs the display clock only when M/S = HIGH and CLS = HIGH. Other than the above: External clock input This pin inputs or outputs the liquid crystal frame signal. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal This pin inputs or outputs the liquid crystal synchronization signal. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal This pin inputs or outputs the field start signal. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal This pin inputs or outputs the drive pattern signal. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal This pin is used to control blanking of liquid crystal display. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal This pin inputs or outputs the line clock. M/S = HIGH: Outputs the signal M/S = LOW: Inputs the signal They output the signal for the segment drive of liquid crystal. They output the signal for common drive of liquid crystal. Number of pins 1 1
CL
I/O
1
FR
I/O
1
SYNC
I/O
1
CA
I/O
1
F1, F2
I/O
1
DOFF
I/O
1
YSCL
I/O
1
SEGn COMn
O O
396 132
10
EPSON
Rev. 1.0
S1D15G10D08B000 7.5 EEPROM Interface Pins
Pin name I/O Description Number of pins 1 1 1
SDA O Connected to the SDA pin of S1F17A10. *1 RESET O Connected to the XRST pin of S1F17A10. *1 CLOCK O Connected to the SCK pin of S1F17A10. *1 * Always open if the S1F17A10 is not used.
7.6 Control Signals
Pin name SLP I/O O Description It is the sleep control pin. It outputs LOW level when the sleep-in command is executed. Number of pins 1
7.7 Test Signals
Pin name TEST1 TEST2 TESTA TESTB TESTC TESTD I/O I O O Description The pin for testing IC chips. Fix this pin to LOW. The output pin for testing IC chips. Make this pin open. The output pin for testing IC chips. Make this pin open. Number of pins 1 1 12
Rev. 1.0
EPSON
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S1D15G10D08B000
8. FUNCTIONAL DESCRIPTION
8.1 MPU Interfaces
8.1.1 Selecting an MPU Interface Type S1D15G10 transfers data via the 8/16-bit bi-directional data bus or serial data input. You can select a desired interface face through the combinations of settings of IF1, IF2 and IF2 as shown in Table 8.1.1. Table 8.1.1 IF1 HIGH HIGH HIGH LOW LOW LOW IF2 HIGH HIGH LOW HIGH LOW LOW IF3 HIGH LOW LOW HIGH HIGH LOW Interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 9-bit serial 8-bit serial CS CS CS CS CS CS CS A0 A0 A0 A0 A0 -- A0 RD E RD RD E E -- -- WR D15 to D8 D7 to D0 SI S C L R/W WR D15 to D8 D7 to D0 -- -- WR -- D7 to D0 -- -- R/W D15 to D8 D7 to D0 -- -- R/W -- D7 to D0 -- -- -- -- -- SI SCL -- -- -- SI SCL -- : Must be fixed to either HIGH or LOW.
8.1.2 8- or 16-bit Parallel Interface S1D15G10 identifies type of the data bus signals according to combinations of A0, RD (E) and WR (R/W) signals as shown in Table 8.1.2. Table 8.1.2 68 series A0 1 1 0 0 R/W 0 1 1 0 E 1 1 1 1 80 series RD 1 0 0 1 WR 0 1 1 0 Function Parameters or display data write. Display data read. Status read. Control data write (command).
Except when the CS=LOW is taking place, D15 to D0 on S1D15G10 are caused to high impedance, disabling input of A0, RD (E) and WR (R/W). Relation between Data Bus and Gradation Data S1D15G10 offers the 256-color display (8 gray-scale) out of 4096 colors as well as the 4096-color display (16 grayscale). When using 256-color display out of 4096 colors, you can specify color for each of R, G and B using the palette function. When using 4096 colors for display, you can select the type A or type B display mode depending on the data bus and RGB you use. Use the data control command for switcing between these modes. (1) 256-color display out of 4096 colors Using RGBSET8 command enables you to set color for each of R, G and B by turning on the palette function prepared to convert 3- or 2-bit data to 4-bit data. 1 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB (8 bits) data is converted to RRRRGGGGBBBB (12 bits) and then stored on the display RAM. 2 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8: RRRGGGBB (8 bits) D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB (8 bits) Data of two pixels is respectively converted to RRRRGGGGBBBB (12 bits) data and then simultaneously written to two addresses on the display RAM.
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S1D15G10D08B000
(2) 4096 color display (2-1) Type 4096 color display 1 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG (8 bits) 1st write D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR (8 bits) 2nd write D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB (8 bits) 3rd write Data is acquired through write operations as shown above and then that of two pixels is written to the display RAM. 2 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX (12 bits) Data is acquired through single write operation and then written to the display RAM. "XXXX" are dummy bits, and they are ignored for display. (2-2) Type B 4096 color display 1 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR (4 bits) 1st write D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB (8 bits) 2nd write A single pixel of data is read after the second write operation as shown, and it is written in the display RAM. "XXXX" are dummy bits, and they are ignored for display. 2 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB (12 bits) A single pixel of data is read and written in the display RAM in a single write operation. "XXXX" are dummy bits, and they are ignored for display. 8.1.3 8- and 9-bit Serial Interface The 8-bit serial interface uses four pins - CS, SI, SCL and A0 - to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins - CS, SI and SCL - for the same purpose. Data read is not available with the serial interface. Data entered must be 8 bits. Refer to the following chart for entering commands, parameters or gray-scale data. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode (described in the preceding section) at every gradation. (1) 8-bit serial interface When entering data (parameters): A0 = HIGH at the rising edge of the 8th SCL.
CS dot0(R) R2 SI SCL 1 A0 2 3 4 5 6 7 8 1 2 3 4 5 6 D7 R1 D6 R0 D5 G2 D4 dot1(G) G1 D3 G0 D2 dot2(B) B1 D1 B0 D0 R2 D7 dot3(R) R1 D6 R0 D5 G2 D4 dot4(R) G1 D3 G0 D2
When entering command: A0 = LOW at the rising edge of the 8th SCL.
CS command SI SCL 1 A0 2 3 4 5 6 7 8 1 2 3 4 5 6 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 command D5 D4 D3 D2
Rev. 1.0
EPSON
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S1D15G10D08B000
(2) 9-bit serial interface When entering data (parameters): SI = HIGH at the rising edge of the 1st SCL.
CS dot0(R) R2 SI SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 D/C D7 R1 D6 R0 D5 G2 D4 dot1(G) G1 D3 G0 D2 dot2(B) B1 D1 B0 D0 D/C R2 D7 dot3(R) R1 D6 R0 D5 D4
When entering commands: SI = LOW at the rising edge of the 1st SCL.
CS command SI SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 D/C D7 D6 D5 D4 D3 D2 D1 D0 D/C command D7 D6 D5 D4
* If CS is caused to HIGH before 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again. * In order to avoid data transfer error due to incoming noise, it is recommended to set CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register. * When executing the command RAMWR, set CS to HIGH after writing the last address (after starting the 9th pulse in case of 9-bit serial input or after starting the 8th pulse in case of 8-bit serial input). Example : In case of 9-bit serial input,
CS G0 SI SCL 7 8 9 1 2 3 4 5 6 7 8 9 D2 B1 D1 B0 D0 D/C R2 D7 R1 D6 R0 D5 G2 D4 G1 D3 G0 D2 B1 D1 B0 D0
14
EPSON
Rev. 1.0
S1D15G10D08B000 8.2 Access to DDRAM and Internal Registers
S1D15G10 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the data read in the dummy cycle is held by the bus holder, and then it is read from the bus holder to the system bus in the succeeding read cycle. Fig. 8.2.1 illustrates these relations. * Write operation
A0 tcyc WR MPU DATA Command write Data write Data write
Bus holder Internal Data write signal
* Read operation
A0 Command write WR Dummy read RD MPU External pulse Data read
Bus holder Internal Data Read signal
Command
RAM data
RAM data
Fig. 8.2.1 * There is a restriction in the read sequence of the DDRAM. Namely, the data at the specified address is not output in the first data read conducted immediately after the memory read command (dummy read). It is read in the second data read.
Rev. 1.0
EPSON
15
S1D15G10D08B000 8.3 DDRAM
8.3.1 DDRAM It is 396 x 132 x 4 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page address and column address. Since display data from MPU - D7 to D0 and D16 to D8 - correspond to one or two pixels of RGB, data transfer-related restrictions are reduced, realizing the display flexibly. The RAM on S1D15G10 is separated to a block per 4 line to allow the display system to process data on the block basis. MPU's read and write operations to and from the RAM are performed via the I/O buffer circuit. Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration. Memory Map (When using the 8 gray-scale. 8-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD read direction
P11:0 P11:1
0 131 R Data P10:1 131 130 129 128 127 126 125 124 123 122 D7 D6 D5 G D4 D3 D2 B D1 D0 R D7 D6 D5
1 130 G D4 D3 D2 B D1 D0 R D7 D6 D5
131 0 G D4 D3 D2 B D1 D0
Color Page Block 0 P10:0 0 1 2 3 1 4 5 6 7 2 8 9
31
124 125 126 127
7 6 5 4 3 2 1 0 1 2 3 4 5 6 394 395 396
32
128 129 130 131
SEGout
Each of RGB data entered to D7 to D0 (3 or 2 bits) is converted to 4 bits before written to the RAM. You can change position of R and B with DATCTL command.
16
EPSON
Rev. 1.0
S1D15G10D08B000
Memory Map (When using the 8 gray-scale, 16-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD P11: 0 read direction Color
Data Page P11: 1 Color Page
0
1
2
3
130
131
R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 D15 D12 D9 D7 D4 D1 D15 D12 D9 D7 D4 D1 D14 D11 D8 D6 D3 D0 D14 D11 D8 D6 D3 D0 D13 D10 131 D5 D2 130 D13 D10 129 D5 D2 128
R1 G1 B1 R2 G2 B2 D15 D12 D9 D7 D4 D1 D14 D11 D8 D6 D3 D0 D13 D10 1 D5 D2 0
R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1
Data D7 D4 D1 D15 D12 D9 D7 D4 D1 D15 D12 D9
R2 G2 B2 R1 G1 B1 D7 D4 D1 D15 D12 D9 D6 D3 D0 D14 D11 D8 D5 D2 D13 D10
D6 D3 D0 D14 D11 D8 D6 D3 D0 D14 D11 D8 Block P10:0 P10:1 D5 D2 D13 D10 D5 D2 D13 D10 0 0 1 2 3 1 4 5 6 7 2 8 9 131 130 129 128 127 126 125 124 123 122
31
124 7 125 6 126 5 127 4
32
128 3 129 2 130 1 131 0
SEGout
1
2
3
4
5
6
7
8
9
10 11 12
391 392 393 394 395 396
Each of RGB data entered to D7 to D0 (3 or 2 bits) is converted to 4 bits before written to the RAM. You can change position of R and B with DATCTL command.
Rev. 1.0
EPSON
17
S1D15G10D08B000
Memory Map (When using the 16 gray-scale Type A, 8-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD P11: 0 read direction Color
Data Page P11: 1 Color Data Page
0
1
2
3
130
131
R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 131 130 129 128
R1 G1 B1 R2 G2 B2 D7 D3 D7 D3 D7 D3 D6 D2 D6 D2 D6 D2 D5 D1 D5 D1 D5 D1 D4 D0 D4 D0 D4 D0 1 0
R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6
R2 G2 B2 R1 G1 B1 D3 D7 D3 D7 D3 D7 D2 D6 D2 D6 D2 D6 D1 D5 D1 D5 D1 D5 D0 D4 D0 D4 D0 D4
D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 Block P10:0 P10:1 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 0 0 1 2 3 1 4 5 6 7 2 8 9 131 130 129 128 127 126 125 124 123 122
31
124 7 125 6 126 5 127 4
32
128 3 129 2 130 1 131 0
SEGout
1
2
3
4
5
6
7
8
9
10 11 12
391 392 393 394 395 396
You can change position of R and B with DATCTL command.
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EPSON
Rev. 1.0
S1D15G10D08B000
Memory Map (When using the 16 gray-scale Type A, 16-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD read direction
P11:0 P11:1
0 131 R Data D15 D14 D13 D12 G D11 D10 D9 D8 B D7 D6 D5 D4 R D15 D14 D13 D12
1 130 G D11 D10 D9 D8 B D7 D6 D5 D4 R D15 D14 D13 D12
131 0 G D11 D10 D9 D8 B D7 D6 D5 D4
Color
Page Block 0 P10:0 0 1 2 3 1 4 5 6 7 2 8 9 P10:1 131 130 129 128 127 126 125 124 123 122
31
124 125 126 127
7 6 5 4 3 2 1 0 1 2 3 4 5 6 394 395 396
32
128 129 130 131
SEGout
You can change position of R and B with DATCTL command
Rev. 1.0
EPSON
19
S1D15G10D08B000
Memory map (when using the 16 gray-scale Type B, 8-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD read direction
P11:0 P11:1
0 131 R Data D3 D2 D1 D0 G D7 D6 D5 D4 B D3 D2 D1 D0 R D3 D2 D1 D0
1 130 G D7 D6 D5 D4 B D3 D2 D1 D0 R D3 D2 D1 D0
131 0 G D7 D6 D5 D4 B D3 D2 D1 D0
Color Page Block 0 P10:0 0 1 2 3 1 4 5 6 7 2 8 9 P10:1 131 130 129 128 127 126 125 124 123 122
31
124 125 126 127
7 6 5 4 3 2 1 0 1 2 3 4 5 6 394 395 396
32
128 129 130 131
SEGout
Positions of R and B can be changed using the DATCTL command.
20
EPSON
Rev. 1.0
S1D15G10D08B000
Memory map (when using the 16 gray-scale Type B, 16-bit mode)
RGB alignment (Command of data control parameter2=000) Column LCD read direction
P11:0 P11:1
0 131 R Data D11 D10 D9 D8 G D7 D6 D5 D4 B D3 D2 D1 D0 R D11 D10 D9 D8
1 130 G D7 D6 D5 D4 B D3 D2 D1 D0 R D11 D10 D9 D8
131 0 G D7 D6 D5 D4 B D3 D2 D1 D0
Color Page Block 0 P10:0 0 1 2 3 1 4 5 6 7 2 8 9 P10:1 131 130 129 128 127 126 125 124 123 122
31
124 125 126 127
7 6 5 4 3 2 1 0 1 2 3 4 5 6 394 395 396
32
128 129 130 131
SEGout
Positions of R and B can be changed using the DATCTL command.
Rev. 1.0
EPSON
21
S1D15G10D08B000
8.3.2 Page Address Control Circuit This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the DDRAM to display image on the LCD. You can specify a scope of the page address (start and end page) with PASET (page address set) command. When the page-direction scan is specified with DATCTL (data control) command and the addresses are incremented from the start up to the end page, the column address is incremented by 1 and the page address returns to the start page. The DDRAM supports up to 132 lines, and thus the total page becomes 132. In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page address is returned to the start page. Using the address normal/inverse parameter of DATCTL command allows you to inverse the correspondence between the DDRAM address and common output. 8.3.3 Column Address Control Circuit This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify a scope of the column address (start and end column) using CASET (column address set). When the column-direction scan is specified with DATCTL command and the addresses are incremented from the start to the end up to the end column, the page address is incremented by 1 and the column address returns to the start column. In the read operation, too, the column address is automatically incremented by 1 and returns to the start page as the end column is reached. Just like the page address control circuit, using the column address normal/inverse parameter of DATCTL command enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement relaxes restrictions in the chip layout on the LCD module. 8.3.4 I/O Buffer Circuit It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU's read or write of the DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while the LCD is turned on does not cause troubles such as flicking of the display images. 8.3.5 Block Address Circuit This circuit associates pages on the DDRAM with COM output. S1D15G10 processes signals for the liquid crystal display on 4-page basis (block basis). Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in block. 8.3.6 Display Data Latch Circuit This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since DISNOR/DISINV (display normal/inverse) and DISON/DISOFF (display on/display off) commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
22
EPSON
Rev. 1.0
S1D15G10D08B000 8.4 Area Scroll Display
Using ASCSET (area scroll set) and SCSTART (scroll start set) commands allows you to scroll the display screen partially. You can select any one of the following four scroll patterns.
Center screen scroll
Top screen scroll
Bottom screen scroll
Whole screen scroll
: Fixed area
: Scroll area
Fig. 8.4.1 When, for example, 1/120 duty (Display area: 30 blocks = 120 lines) is selected, and the top 2 blocks = 8 lines and bottom 2 blocks = 8 lines are specified as the fixed areas and the remaining 26 blocks = 104 lines as the scroll area, 3 blocks = 12 lines on the DDRAM can be used as the background area.
DDRAM block
0 1 2
LCD panel
30 blocks =128 line
27 28
30 31 32 Fixed area Display area Scroll area Background area
Rev. 1.0
EPSON
23
S1D15G10D08B000 8.5 Partial Display
Using PTLIN (partial in) command allows you to turn on the partial display (division by line) of the screen. This mode requires less current consumption than the whole screen display, making it suitable for the mobile equipment in the standby state.
: Display area (partial display area)
: Non-display area
8.6 Gray-Scale Display
This function represents gray-scale by frame modulating the gray-scale date written on the display data RAM. In the 256-out-of-4096 colors (8 gray-scale) display, you can specify display colors using the command.
Normally black liquid crystal in the reverse display mode - 8 gray scale display
R (D7,D6,D5) Black (0,0,0) Red (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1)
G (D4,D3,D2)
Black (0,0,0)
Green (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1)
B (D1,D0)
Black (0,0)
Blue (0,1) (0,1) (0,1) (1,0) (1,0) (1,0) (1,1)
Any one of above
Any one of above
Respective data on red, green and blue are converted to the display data to be specified by the parameters of RGBSET8 command, and then written to the DDRAM. Blue is displayed in 4 gray-scale.
8.7 Oscillation Circuit
S1G15G10 contains the oscillation circuit whose operation does not require any external part. The oscillation circuit is enabled only when M/S = HIGH and CLS = HIGH. When the external clock signal is (CLS = LOW or M/S = LOW), the clock is entered from CL pin.
8.8 Display Timing Generation Circuit
This circuit generates the timing signal for display (CL, FR, SYNC, CA, F1, F2, DOFF) using the clock from the builtin oscillation circuit or the external clock. It is also used to generate the clock to turn on the liquid crystal-drive power circuit. When using S1D15G10 in multi-chip array, the display timing signal (CL, FR, SYNC, CA, F1, F2, DOFF) must be sent from the master to the slave.
8.9 SEG Decoder Circuit
This circuit outputs the segment driver control signal based on display data for 4-page and the timing signal.
8.10 Liquid Crystal Drive Circuit
It outputs liquid crystal drive voltage. Responding to the decoder output signal and the display-timing signal, the segment output pin outputs one of potentials V2, V1, VC, MV1 or MV2 and the common output pin outputs one of potentials V3, VC or MV3. 24
EPSON
Rev. 1.0
S1D15G10D08B000 8.11 Liquid Crystal-Drive Power Circuit
The power circuit contained in S1D15G10 generates voltage required to drive liquid crystal. This low power consumption type power circuit is consisted the voltage regulator, booster circuits (primary, secondary) and voltage follower. The power circuit is enabled only when the master operation mode is turned on. The power control circuit turns on or off the voltage regulator, booster circuits, Reference voltage generation circuit and voltage follower responding to PWRCTR (power control set) command. Thus, function of the external and internal power supplies can be partly used in parallel. Table 8.11.1 lists the functions controlled by the 4-bit data - parameter of PWRCTR. Table 8.11.2 shows combinations of 4 bits (combinations shown in Table 8.11.2 alone are valid). Table 8.11.1 Item D3 D2 D1 D0 Primary booster circuits control bit Secondary booster circuit control bit Reference voltage generation circuit control bit Voltage adjusting circuit/Voltage follower control bit "1" ON ON ON ON State "0" OFF OFF OFF OFF
Table 8.11.2 Function turned on 1. Entire built-in power circuit is turned on 2. Other than the secondary booster and step-down circuits 3. External power supply alone D3 1 1 0 D2 1 0 0 D1 1 1 0 D0 External power input pins 1 - 1 V3, MV3 0 V3, V2, VC, MV1, MV3
8.11.2 Voltage Transform Circuit The charge pump booster circuit and the operational amplifier's voltage follower generate each potential required to drive the liquid crystal based on the reference voltage generated by the voltage regulator. Ground potentials (abbreviated as GND in the following description) of the power circuit in the IC are GND2 and GND4. Fig. 8.11.1 illustrates mutual relationship between potentials.
Primary boorster circuit
VCLS
Secondary boorster circuit
V3
V2 V2 V1, VC, MV1, generation circuit V1 VDD2 VC MV1 GND MV2
Secondary boorster circuit
MV3
Fig. 8.11.1 Mutual Relationship between Voltage Transform Circuits
Rev. 1.0
EPSON
25
S1D15G10D08B000
Table 8.11.3 shows the theoretical expression of respective potentials. Since these are theoretical values, they can differ from actual voltages depending on load on the liquid crystal. Table 8.11.3 Theoretical Expression of Potentials Signal name V3 V2 V1 VC MV1 GND(MV2) MV3 Theoretical expression (relative to GND = 0V) 2x(V2-GND) 4/3x(V1-GND) Output from voltage regulator 2/3x(V1-GND) 1/3x(V1-GND) 0V -(V1-GND) Theoretical expression (relative to VC = 0V) 2x(VC-GND) VC-GND 1/2x(VC-GND) 0V -1/2x(VC-GND) -(VC-GND) -2x(VC-GND)
8.11.3 Primary Booster Circuit The built-in booster circuit double the voltage of VDD2-GND. VDD2-GND voltage is double by capacitor C connected across CAP1+ and CAP1 as well as VCSL and GND (or VDD2), and then output at VCSL pin. Fig. 8.11.2 shows how the voltage is stepped up by the capacitors connected.
VCSL=2xVDD2 GND or VDD2 C + VCSL
C +
CAP1- CAP1+
VDD2
GND
Fig. 8.11.2 Relation between Capacitors and Voltage Step-up
8.11.4 Voltage Regulator Circuit The voltage regulator circuit generates the liquid crystal drive voltage V1 using VCSL from the primary booster circuit. S1D15G10 incorporates the high-precision constant voltage source, 64-step electronic volume control function and resistor to regulate V1 voltage. The voltage regulator circuit covers a wider temperature range with fewer numbers of parts thanks to the temperature gradient control function as well as the temperature sensing function. However, capacitors may be required for voltage regulation between V1 and GND pins due to the load of LCD panel. Insert the capacitors, if necessary, by observing the voltage waveforms and current consumption. (A) Built-in Resistor for V1 Voltage Regulation Using this resistor and the electronic volume control function allows you to control the liquid crystal drive voltage V1 to an optimum level for the LCD panel with the command alone, without resorting to external resistors. V1 output voltage can be determined from Equation A-1 as long as the relation V1 < VCSL is met. However, set the voltage of V1 by allowing for a drop in the voltage due to load, so that it becomes at or below 80 % of VCSL.
Rb Rb + 2 V 1 = 1 + * VEV = 1 + * 1- * VREG (Equation A-1) Ra Ra 218
Note: VREG is the constant voltage source inside the IC. It is 1.2V (Typ.) at Ta = 25C.
26
EPSON
Rev. 1.0
S1D15G10D08B000
VCSL
VEV (Constant voltage source + Electronic volume controller) Built-in Rb
V1
Built-in Ra GND
Fig. 8.11.3 Voltage Regulator Circuit Rb/Ra in Equation A-1 is the resistance ratio of the built-in V1 voltage-regulating resistance. This ratio can be varied in 8 levels by changing parameters 2(P2) of electronic volum control command. Reference ratios of "1 + Rb/Ra" are shown in Table 8.11.4. Table 8.11.4 Resistance Ratio of Built-in V2 Voltage-Regulating Resistance: Parameters and "1+ R/Ra" Ratio (For reference) Parameter P22 P21 P20 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1+Rb/Ra ratio 2.9032 3.1914 3.4090 3.6585 3.8793 4.0909 4.3269 4.5454 V1 voltage value Small * * * * Large
(B) V1 voltage control external resistor If you use an external resistance control model, you can set the V1 voltage using an external resistor. Use a semi-fixed resistor for V1 voltage regulation.
VCSL VEV (Fixed voltage source and Electronic volume control) + - VR External resistor Rb External resistor Ra GND GND V1
Fig. 8.11.4 Voltage Regulator Circuit Select the external Ra and Rb values to allow stable voltage supply by observing the V2 voltage waveforms. As the VR pin has a high input impedance and it is susceptible to ambient noise, the resistors and their leads must be placed in a short distance and they must be away from the clock source. (C) Constant Voltage Source and Electronic Volume Control Circuit The constant voltage source generates VREG - the reference voltage inside the IC. You can specify one of four types of temperature gradients with parameters of electronic volum control command. See Fig. 8.11.5.
Rev. 1.0
EPSON
27
S1D15G10D08B000
Table 8.11.5 Parameters and VREG Temperature Gradient Parameter Temperature gradient (%/C) 0 0 -0.05 0 1 -0.1 1 0 -0.15 1 1 -0.2 The electronic volume control circuit varies in Equation A-1 according to parameters 1(P1) of electronic volum control command. Table 8.11.6 lists relation between the parameters and . Table 8.11.6 Parameters and Electronic Volume Parameter P15 P14 P13 P12 P11 P10 0 0 0 0 0 0 63 0 0 0 0 0 1 62 0 0 0 0 1 0 61 * * * * * * 1 1 1 1 0 1 2 1 1 1 1 1 0 1 1 1 1 1 1 1 0
V1 voltage value Small
* * *
Large
8.11.5 Voltage Divider/Voltage Follower Circuit The voltage divider/voltage follower circuit V1 output from the voltage regulator circuit and then generates liquid crystal drive voltages VC using the operational amplifier-featured voltage follower. Capacitors may be required for voltage regulation between the GND and each of VC pin due to the load of LCD panel. Insert the capacitors, if necessary, by observing the voltage waveforms and current consumption. The following theoretical equation is the potential relationship. When the capacitor C is connected between CAP2+ and CAP2- and between V2 and GND, the primary booster boosts the voltage from V1 and MV1 and generates V2. VC = 2/3 x V1 MV1 = 1/3 x V1 V2 = 4/3 x V1 8.11.6 Secondary Booster Circuit / Step-Down Circuit The secondary booster/step-down circuit boosts or steps down based on V2, GND and produces V3 and MV3. Their potential relationship is expressed with the following theoretical equation: V3 = 2xV2 MV3 = -V2
28
EPSON
Rev. 1.0
S1D15G10D08B000
8.11.7 Samples of Connections Peripheral to Power Circuit (For your information) Following illustrates the connections when the entire power circuit is used.
C1 C1 + + CAP1+ CAP1- CAP2+ CAP2- CAP3+ CAP3- CAP4+ CAP4- CAP5+ CAP5- VDD2 VCSL GND V3 V2 V1 VC MV1 MV3 + C2 2 + + C1 2
Sample of common setting Item C1 C2 Setting 1.0 to 4.7 0.47 to 1.0 Unit F
C1 C1
+ +
+
Optimum values of C1 and C2 above vary depending on the LCD panel to be driven. Above values should be referenced as information only. It is recommended to check how patterns with high load are displayed before finalizing the values. C between VDD2 and GND signifies a bias capacitor.
Rev. 1.0
EPSON
29
S1D15G10D08B000
9. COMMANDS
9.1 Command List
Following table lists the control signals and commands using the 80 series interface as the example. Command 1 DISON 2 DISOFF 3 DISNOR 4 DISINV 6 DISCTL 7 SLPIN 8 SLPOUT 9 PASET 10 CASET 11 DATCTL 13 RAMWR 14 RAMRD 15 PTLIN 16 PTLOUT 17 RMWIN 19 ASCSET 21 OSCON 22 OSCOFF 24 VOLCTR 25 VOLUP 27 TMPGRD 28 EPCTIN 29 EPCOUT 30 EPMWR 31 EPMRD A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 Function Display on Display off Normal display Inverse display Common scan direction Display control Sleep in Sleep out Page address set Column address set Data scan direction, etc. 256-color position set Writing to memory Reading from memory Partial display in Partial display out Read and modify write End Area scroll set Scroll start set Internal oscillation on Internal oscillation off Power control Electronic volume control Hex Parameter AF AE A6 A7 BB CA 95 94 75 15 BC CE 5C 5D A8 A9 E0 EE AA AB D1 D2 20 81 None None None None 1byte 3byte None None 2byte 2byte 3byte 20byte Data Data 2byte None None None 4byte 1byte None None 1byte 2byte None None 14byte 1byte None None None None None None
5 COMSCN 0
12 RGBSET8 0
18 RMWOUT 0 20 SCSTART 0
23 PWRCTR 0
Increment electronic control by 1 D6 Decrement electronic control by 1 D7 Temperature gradient set Control EEPROM Cancel EEPROM control Write into EEPROM Read from EEPROM Read register 1 Read register 2 NOP instruction Status read 82 CD CC FC FD 7C 7D 25
26 VOLDOWN 0
32 EPSRRD1 0 33 EPSRRD2 0 34 NOP 35 STREAD 0 0
Status
30
EPSON
Rev. 1.0
S1D15G10D08B000
(1) Display ON (DISON) Command: 1 Parameter: None It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated at the level corresponding to the display data and display timing. You can't turn on the display as long as the sleep mode is selected. Thus, whenever using this command, you must cancel the sleep mode first. A0 0 RD WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1
Command
(2) Display OFF (DISOFF) Command: 1 Parameter: 0 It is used to forcibly turn the display off. As long as the display is turned off, every segment and common outputs are forced to VC level and DOFF pin is caused to LOW. A0 0 RD WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
Command
(3) Normal display (DISNOR) Command: 1 Parameter: 0 It is used to normally highlight the display area without modifying contents of the display data RAM. Command A0 0 RD WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0
(4) Inverse display (DISINV) Command: 1 Parameter: 0 It is used to inversely highlight the display area without modifying contents of the display data RAM. This command does not invert non-display areas in case of using partial display. Command A0 0 RD WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1
(5) Common scan (COMSCAN) Command: 1 Parameter: 1 It is used to specify the common output scan direction. This command helps increasing degrees of freedom of wiring on the LCD panel. A0 Command 0 Parameter1 (P1) 1 RD WR 1 0 1 0 D7 1 * D6 0 * D5 1 * D4 1 * D3 D2 D1 D0 1 0 1 1 * P12 P11 P10 Function -- Common scan direction
When 1/132 is selected for the display duty, pins and common output are scanned in the order shown below. P12 0 0 0 0 P11 0 0 1 1 P10 0 1 0 1 COM1 pin 1 1 68 68 Common scan direction COM68 pin COM69 pin 68 69 68 132 1 69 1 132 COM132 pin 132 69 132 69

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(6) Display control (DISCTL) Command: 1 Parameter: 3 This command and succeeding parameters are used to perform the display timing-related setups. This command must be selected before using SLPOUT. Don't change this command while the display is turned on. A0 0 1 RD WR 1 0 1 0 D7 1 * D6 1 * D5 D4 D3 D2 D1 D0 Function 0 0 1 0 1 0 -- * P14 P13 P12 P11 P10 CL dividing ratio, F1 and F2 drive pattern. P25 P24 P23 P22 P21 P20 Drive duty * P34 P33 P32 P31 P30 FR inverse-set value * * * * * P40 Dispersion/non-dispersion
Command Parameter1 (P1)
Parameter2 (P2) 1 1 0 * * Parameter3 (P3) 1 1 0 * * Parameter4 (P4) 1 1 0 * * *: Invalid bits irrelevant to the operation.
P1: It is used to specify the CL dividing ratio, F1 and F2 drive-pattern switching period. P14, P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock. P14 0 0 0 0 P13 0 0 1 1 P12 0 1 0 1 CL dividing ratio 2 divisions (default) 4 divisions 8 divisions Not divide
P11, P10: They are used to change F1 and F2 drive-pattern switching period. P11 0 0 1 1 P10 0 1 0 1 F1, F2 switching period 8H (default) 4H 16H Field
P2: It is used to specify the duty of the module on block basis. Duty Example: 1/128 duty * 0 * 0 P25 P24 P23 P22 P21 P20 0 1 1 1 1 1 (Numbers of display lines)/4-1 128/4-1=31
P3: It is used to specify number of lines to be inversely highlighted on LCD panel from P33 to P30 (lines can be inversely highlighted in the range of 2 to 16) Inversely highlighted lines Example: 11H Example: 13H * 0 0 * 0 0 * 0 0 P34 P33 P32 P31 P30 0 1 0 1 0 0 1 1 0 0 Inversely highlighted lines -1 11-1=10 13-1=12
In the default, 11H inverse highlight is selected. P34= "0": Inversion occurs every frame. P34= "0": Independent from frames P4: It is used to set dispersion or non-dispersion for the LCD driving method. P40= "0": Dispersion P40= "1": Non-dispersion (7) Seep in (SLPIN) Command: 1 Parameter: 0 Entering this command generates LOW at SLP pin. Command A0 0 RD WR 1 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 1
DOFF (LCD panel blanking control pin) on S1D15G10 is caused to LOW when the sleep in mode is turned on.
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(8) Sleep out (SLPOUT) Command: 1 Parameter: 0 Entering this command generates HIGH at SLP pin. Command A0 0 RD WR 1 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 0
(9) Page address set (PASET) Command: 1 Parameter: 2 When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the column address is incremented by 1 and the page address is returned to the start page. Note that the start and end page must be specified as a pair. Also, the relation "start page < end page" must be maintained. A0 Command 0 Parameter1 (P1) 1 Parameter2 (P2) 1 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 1 0 1 0 1 1 0 P17 P16 P15 P14 P13 P12 P11 P10 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Function -- Start page End page
(10) Column address set (CASET) Command: 1 Parameter: 2 When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the column address area. As the addresses are incremented from the start to the end column in the column-direction scan, the page address is incremented by 1 and the column address is returned to the start column. Note that the start and end page must be specified as a pair. Also, the relation "start column < end column" must be maintained. A0 Command 0 Parameter1 (P1) 1 Parameter2 (P2) 1 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 1 0 1 0 1 1 0 P17 P16 P15 P14 P13 P12 P11 P10 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Function -- Start address End address
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(11) Data control (DATCTL) Command: 1 Parameters: 2 This command and succeeding parameters are used to perform various setups needed when MPU operates display data stored on the built-in RAM. A0 Command 0 Parameter1 (P1) 1 RD WR 1 0 1 0 D7 1 * D6 0 * D5 1 * D4 1 * D3 D2 D1 D0 Function 1 1 0 0 -- * P12 P11 P10 Normal/inverse display of page address and page-address scan direction. * * * P20 RGB arrangement * P32 P31 P30 Gray-scale setup
Parameter2 (P2) Parameter3 (P3)
1 1
1 1
0 0
* *
* *
* *
* *
P1: It is used to specify the normal or inverse display of the page address and also to specify the page address scanning direction. P10: Normal/inverse display of the page address. P10 = 0: Normal and P10 = "1": Inverse. P11: Normal/reverse turn of column address. P11 = "0": Normal rotation and P11 = "1": Reverse rotation P12: Address-scan direction. P12 = "0": In the column direction and P12 = "1": In the page direction. P2: RGB arrangement. This parameter allows you to change RGB arrangement of the segment output according to RGB arrangement on the LCD panel. In this case, writing position of data {R = (D7, D6, D5), G = (D4, D3, D2), B = (D1, D0)} on the display memory is changed.
P20
line Even page Odd page 1 2
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 R R B B G G G G B B R R R R B B G G G G B B R R R R B B G G G G
*** *** *** *** ***
SEG395
0 1
B B R R
In the default, (P20) = (0) is selected. P3: Gray-scale setup. Using this parameter, you can a select desired display colors between the 256 colors (8 gray-scale) or 4096 colors (16 gray-scale) for the display color. For 16 gray-scale display, you can select the Type A or Type B display mode depending on the difference in RGB data arrangement you use. P32 P31 P30 0 0 1 0 1 0 1 0 0 Numbers of gray-scale 8 gray-scale 16 gray-scale display Type A 16 gray-scale display Type B
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(12) 256-color position set (RGBSET8) Command: 1 Parameter: 0 When turning on 256-color display (8 gray-scale), this command allows you to choose colors to represent each of red, green and blue from 4096 colors. A0 0 1 1 1 1 1 1 RD WR 1 0 1 0 1 1 1 1 1 0 0 0 0 0 D7 1 * * * * * * D6 1 * * * * * * D5 0 * * * * * * D4 D3 D2 D1 D0 Function 0 1 1 1 0 -- * P13 P12 P11 P10 Intermediate red tone 000 * * * * * P83 P82 P81 P80 Intermediate red tone 111 P93 P92 P91 P90 Intermediate green tone 000 P163 P162 P161 P160 Intermediate green tone 111 P173 P172 P171 P170 Intermediate blue tone 00 P203 P202 P201 P200 Intermediate blue tone 11
Command Parameter1 (P1) Parameter4 (P8) Parameter9 (P9) Parameter16 (P16) Parameter17 (P17) Parameter20 (P20)
Data (Red and Green: 3 bits and Blue: 2 bits) to be written from the MPU to the DDRAM are converted to 4-bit data before the write operation takes place. When reading data from the DDRAM, data on red and green are converted to 3 bits and that on blue are converted to 2 bits before the output. (13) Memory write (RAMWR) Command: 1 Parameter: Numbers of data written When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command always sets the page and column addresses at the start address. You can rewrite contents of the display data RAM by entering data succeeding to this command. At the same time, this operation increments the page or column address as applicable. The write mode is automatically cancelled if any other command is entered. 1 8-bit bus A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function Command 0 1 0 0 1 0 1 1 1 0 0 -- Parameter 1 1 0 Data to be written Data to be written 2 16-bit bus Command name A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 * * * * * * * * 0 1 0 1 1 1 0 0 Data to be written 1 1 0 Data to be written Function Memory write Write data
(14) Memory read (RAMRD) Command: 1 Parameter: Numbers of data read When MPU reads data from the display memory, this command turns on the data read mode. Entering this command always sets the page and column addresses at the start address. After entering this command, you can read contents of the display data RAM. At the same time, this operation increments the page or column address as applicable. The data read mode is automatically cancelled if any other command is entered. 1 8-bit bus Command Parameter A0 0 1 RD WR 1 0 0 1 D7 0 D6 1 D5 D4 D3 D2 0 1 1 1 Data to be read D1 0 D0 1 Function -- Data to be read
2 16-bit bus Command name A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 * * * * * * * * 0 1 0 1 1 1 0 1 Data to be read 1 0 1 Data to be read
Function Memory read Read data
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(15) Partial in (PTLIN) Command: 1 Parameter: 2 This command and succeeding parameters specify the partial display area. This command is used to turn on partial display of the screen (dividing screen by lines) in order to save power. Since S1D15G10 processes the liquid crystal display signals on 4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis). A0 Command 0 Parameter1 (P1) 1 Parameter2 (P2) 1 RD WR 1 0 1 0 1 0 D7 1 * * D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 * P15 P14 P13 P12 P11 P10 * P25 P24 P23 P22 P21 P20 Function -- Start block address End block address
*: Invalid bits irrelevant with the operation. A block address that can be specified for the partial display must be the displayed one (don't try to specify an address not to be displayed when scrolled). When the partial display mode is turned on, following state is introduced to S1D15G10 in the non-display area: * LOW is output to DOFF pin. * All COM pins output VC. * All SEG pins output V1 or MV1. SEG output is forced to V1 or MV1 depending on state of FR in the last display line. When FR is HIGH, V1 is output and when FR is LOW, MV1 is output. Phase of FR is constantly reversed at start of a frame. (16) Partial out (PTLOUT) Command: 1 Parameter: 0 This command is used to exit from the partial display mode. Command A0 0 RD WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1
(17) Read modify write in (RMWIN) Command: 1 Parameter: 0 This command is used along with the column address set command, page address set command and read modify write out command. This function is used when frequently modifying data to specify a specific display area such as blinking cursor. First set a specific display area using the column and page address commands. Then, enter this command to set the column and page addresses at the start address of the specific area. When this operation is complete, the column (page) address won't be modified by the display data read command. It is incremented only when the display data write command is used. You can cancel this mode by entering the read modify write out or any other command. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
Page address set No Column address set Is modification complete? Yes Read modify write in Read modify write out
Dummy read
Data read
Data write
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(18) Read modify write out (RMWOUT) Command: 1 Parameter: 0 Entering this command cancels the read modify write mode. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
(19) Area scroll set (ASCSET) Command: 1 Parameter: 4 It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and succeeding parameters specify the type of area scroll, FIX area and scroll area. Command Parameter1 (P1) Parameter2 (P2) Parameter3 (P3) Parameter4 (P4) A0 0 1 1 1 1 RD WR 1 0 1 0 1 0 1 0 1 0 D7 1 * * * * D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 * P15 P14 P13 P12 P11 P10 * P25 P24 P23 P22 P21 P20 * P35 P34 P33 P32 P31 P30 * * * * * P41 P40 Function -- Top block address Bottom block address Number of specified blocks Area scroll mode
*: Invalid bits irrelevant with the operation. P4: It is used to specify an area scroll mode. P41 0 0 1 1 P40 0 1 0 1 Types of area scroll Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
Top screen scroll Bottom screen scroll Whole screen scroll
Center screen scroll
: Fixed area
: Scroll area
Since S1D15G10 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas are also specified on the four-line basis (block basis). DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0 block. DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting with 41st block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background areas. P1: It is used to specify the top block address of the scroll + background areas. Specify the 0th block for the top screen scroll or whole screen scroll. The scroll start block address is also set at this top block address until the scroll-start block set command specifies the address. P2: It specifies the bottom address of the scroll + background areas. Specify the 32th block for the bottom or whole screen scroll. Required relation between the start and end blocks (top block address < bottom block address) must be maintained. P3: It specifies a specific number of blocks {Numbers of (Top FIX area + Scroll area) blocks - 1}. When the bottom scroll or whole screen scroll, the value is identical with P2. You can turn on the area scroll function by executing the area scroll set command first and then specifying the display start block of the scroll area with the scroll start set command. Rev. 1.0
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[Area Scroll Setup Example] In the center screen scroll of 1/120 duty (display range: 120 lines = 30 blocks), if 8 lines = 2 blocks and 8 lines = 2 blocks are specified for the top and bottom FIX areas, 104 lines = 26 blocks is specified for the scroll areas, respectively, 12 lines = 3 blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown below. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 P1 1 1 0 * * 0 0 0 0 1 0 Top block address = 2 P2 1 1 0 * * 0 1 1 1 1 0 Bottom block address = 30 P3 1 1 0 * * 0 1 1 0 1 1 Number of specific blocks = 27 P4 1 1 0 * * * * * * 0 0 Area scroll mode = Center *: Invalid bits irrelevant to the operations. (20) Scroll start address set (SCSTART) Command: 1 Parameter: 1 This command and succeeding parameter are used to specify the start block address of the scroll area. Note that you must execute this command after executing the area scroll set command. Scroll becomes available by dynamically changing the start block address. Command Parameter1 (P1) A0 0 1 RD WR 1 0 1 0 D7 1 * D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 1 * P15 P14 P13 P12 P11 P10 Function -- Start block address
*: Invalid bits irrelevant to the operations. (21) Internal oscillation on (OSCON) Command: 1 Parameter: 0 This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS = HIGH is used. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1
(22) Internal oscillation off (OSOFF) Command: 1 Parameter: 0 It turns off the internal oscillation circuit. This circuit is turned off in the reset mode. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0
(23) Power control set (PWRCTR) Command: 1 Parameter: 1 This command is used to turn on or off the liquid crystal driving power circuit, booster/step-down circuits and voltage follower circuit. A0 Command 0 Parameter1 (P1) 1 RD WR 1 0 1 0 D7 0 * D6 0 * D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 * P14 P13 P12 P11 P10 Function -- LCD drive power
*: Invalid bits irrelevant to the operations. P10: It turns on or off the Reference voltage generation circuit. P10 = "1": ON. P10 = "0": OFF. P11: It turns on or off the voltage regulator and circuit voltage follower. P11 = "1": ON. P11 = "0": OFF. Note: 2 bits of P10 and P11 must be turned on or off simultaneously. P12: It turns on or off the secondary booster/step-down circuit. P12 = "1": ON. P12 = "0": OFF. P13: It turns on the primary booster circuit. P13 = "1": ON. P13 = "0": OFF. P14: It is used to select either external resistance using the VR terminal or control via EEPROM access to adjust V1 voltage. P14 = "1": External resistance P14 = "0": EEPROM
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(24) Electronic volume control (VOLCTR) Command: 1 Parameter: 2 This command is used to specify the voltage regulator circuit's electronic volume value and resistance ratio of builtin voltage regulating resistor. A0 Command 0 Parameter1 (P1) 1 Parameter2 (P2) 1 RD WR 1 0 1 0 1 0 D7 1 * * D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 * P15 P14 P13 P12 P11 P10 * * * * P22 P21 P20 Function V1 volume value 1 + Rb/Ra
*: Invalid bits irrelevant to the operations. P1: It is used to specify V1 electronic volume value. P2: It specifies resistance ratio of the internal resistor. (25) Increment Electronic Control (VOLUP) Command: 1 Parameter: No This command increments Electronic Control value of voltage regulator circuit by 1. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0
If you set the Electronic Control value to 111111, the control value is set to 000000 after this command has been executed. (26) Decrement Electronic Control (VOLDOWN) Command: 1 Parameter: No This command decrements Electronic Control value of voltage regulator circuit by 1. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 1
If you set the Electronic Control value to 000000, the control value is set to 111111 after this command has been executed. (27) Temperature Gradient Setting (TMPGRD) Command : 1, Parameter : 14 The average temperature gradient of the voltage for a liquid crystal drive voltage is set up with this command. Set parameters P2 to P14 as in a table below. A0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RD WR 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D7 1 * 0 0 0 0 * * * * * * * * * D6 0 * 0 0 0 0 * * * * * * * * * D5 0 * 0 0 0 0 0 0 0 0 0 0 0 * 0 D4 0 * 0 0 0 0 0 0 0 0 0 0 0 * 0 D3 0 * 0 0 0 0 0 0 0 0 0 0 0 * 0 D2 D1 D0 Function 0 1 0 * P11 P10 Average temperature gradient 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * 0 0 0 0
Command Parameter1 (P1) Parameter2 (P2) Parameter3 (P3) Parameter4 (P4) Parameter5 (P5) Parameter6 (P6) Parameter7 (P7) Parameter8 (P8) Parameter9 (P9) Parameter10 (P10) Parameter11 (P11) Parameter12 (P12) Parameter13 (P13) Parameter14 (P14)
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P1: It specifies average temperature gradient. P11 0 0 1 1 P10 0 1 0 1 Average temperature gradient [%/C] -0.05 -0.1 -0.15 -0.2
P2 to P14: Set the parameter as the table shown previously. (28) Control EEPROM (EPCTIN) Command: 1 Parameter: 1 This command with its parameter selects the EEPROM (S1F17A10) Control mode. The parameter can be set to either Write or Read. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function Command 0 1 0 1 1 0 0 1 1 0 1 -- Parameter1 (P1) 1 1 0 * * P5 * * * * * Selects Write or Read. * Invalid bit; it is ignored during operation. P5: Specifies data writing into or reading from the EEPROM (S1F17A10) as follows. If P5=0: Read; if P5=1: Write (29) Cancel EEPROM Control (EPCOUT) Command: 1 Parameter: 0 This command cancels the EEPROM (S1F17A10) Control mode. If data is read from the EEPROM, both of Electronic Control value and built-in resistance ratio are updated by the read data. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
(30) Write Into EEPROM (EPMWR) Command: 1 Parameter: 0 This command writes the Electronic Control value and built-in resistance ratio into the EEPROM (S1F17A10). Command A0 0 RD WR 1 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
(31) Read From EEPROM (EPMRD) Command: 1 Parameter: 0 This command reads the Electronic Control value and built-in resistance ratio from the EEPROM (S1F17A10), and temporarily stores them in S1D15G10 registers. Command A0 0 RD WR 1 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
(32) Read Register 1 (EPSRRD1) Command: 1 Parameter: 0 Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the Electronic Control value. Command A0 0 RD WR 1 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the STREAD (Status Read) command. (33) Read Register 1 (EPSRRD2) Command: 1 Parameter: 0 Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the built-in resistance ratio. Command A0 0 RD WR 1 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the STREAD (Status Read) command.
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(34) Non-operating (NOP) Command: 1 Parameter: 0 This command does not affect the operation. Command A0 0 RD WR 1 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to prevent malfunctioning due to noise and such. (35) Status read (STREAD) It is the command for reading the internal condition of the IC. Three statuses can be displayed depending on the setting. Command A0 0 RD WR 0 1 D7 D6 D5 D4 D3 Status data D2 D1 D0
1 Status after reset or after NOP operation D7: Area scroll mode Refer to P41 (ASCSET). D6: Area scroll mode Refer to P40 (ASCSET). D5: Read modify write 0: Out 1: In D4: Scan direction 0: Page 1: Column D3: Display ON/OFF 0: OFF 1: ON D2: EEPROM access 0: Out of access 1: In access D1: Display normal/inverse 0: Inverse 1: Normal D0: Partial display 0: OFF 1: ON 2 Status after EPSRRD1 operation D7, D6: Undefined (1 or 0) D5 to D0: Electronic volume control values 3 Status after EPSRRD2 operation D7 to D3: Undefined (1 or 0) D2 to D0: Built-in resistance ratio
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10. ABSOLUTE MAXIMUM RATING
Item Source voltage (1) Input source voltage Source voltage (2) Source voltage (3) Input voltage Output voltage Operating temperature Storage temperature Bare chip Symbol VDD,VDD2 VDDI V3,VOUT V2,V1,VC MV1 MV3 VIN VO Topr Tstr Rating -0.3 to 4.0 -0.3 to 4.0 -0.3 to 25.0 -0.3 to V3 -0.3 to VDD2 -10.0 to +0.5 -0.3 to VDDI+0.5 -0.3 to VDDI+0.5 -40 to +85 -65 to +150 V V C C V Unit V V V
Potential Relation
V3 VOUT VDD2, VDD VCC VDDI V1 V2, VC, MV1
GND
GND
MV2 MV3
System (MPU) side
S1D15G10 side
Notes: 1. Voltages are all indicated relevant to GND = 0V. 2. Voltage of V3, V2, V1, VC, MV1, MV2 (GND) and MV3 must constantly meets the requirement V3 V2V1VCMV1MV2 (GND) MV3. 3. VDD and VOUT voltages must constantly meets the requirement VOUTVDD. 4. If LSI is operated beyond the absolute maximum rating, it can be damaged permanently. Normal operating conditions should conform to the electric characteristics of LSI, otherwise malfunctioning of LSI can result in addition to deterioration of its reliability. 5. Definition of VDD is applicable to VDD3, VDD4 and VDD5 pins. 6. Definition of GND is applicable to GND2, GND3 and GND4 pins.
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11. ELECTRIC CHARACTERISTICS
11.1 DC Characteristics
Except where otherwise specified, GND = 0V, VDD = 2.75V, VDDI = 1.8V and Ta = 20C to 85C. Table 11.1 Item Operating Operable voltage (1) Operating Operable voltage (2) Operating Operable voltage (3) Operable Operable Operable Operable Operable Operable Operable High level input voltage Low level input voltage High level output voltage Low level output voltage Input leak current Output leak current Liquid crystal drive ON resistance Static current consumption Symbol VDD VDDI V3 V3 V2 V1 VC MV1 MV2 MV3 VIHC VILC VOH VOL ILI ILO RONseg V2=5.0V, V=0.5V RONcom V3=16.0V, V=0.5V IDDQ I3Q I2Q Dynamic current consumption IDD VDD=VDDI=3.6V,Ta=25C V3-MV3=18.0V,Ta=25C V2=6.0V,Ta=25C During RAM access 3MHz During display Frame frequency 180Hz VDDI Input terminal capacity Output terminal capacity Oscillated frequency Internal oscillation External input CI CO fOSC fCL During display on Freq.=1MHz Ta=25C, Elemental chip 180Hz device, Ta=25C 180Hz device, 1/132duty -- -- V3 to MV3 -- -- -- -- -- -- -- -- -- IOH=-0.6mA IOL=+0.6mA VIN=VDDI or GND Condition Standard value Min. Typ. Max. 2.6 1.7 12.0 8.0 4.0 3.0 2.0 1.0 GND -7.0 0.8xVDDI 0.7xVDDI 0.0 0.0 VDDI-0.4 0.0 -- -- -- -- -- -- -- -- -- -- -- -- 45.2 -- 2.75 1.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 0.4 2 -- -- 500 180 5 -- -- 47.6 47.6 3.6 VDD 21.0 14.0 7.0 5.3 3.5 1.8 GND -4.0 VDDI VDDI 0.2xVDDI 0.3xVDDI VDDI 0.4 1.0 1.0 10 1.0 10 1.5 3.0 750 400 20 15 15 50.0 -- Unit Applicable pin V V V V V V V V V V V V V V V V A A k k A A A A A A pF pF kHz kHz VDD *1 VDDI V3 V3 V2 V1 VC MV1 MV2 MV3 *2 *3 *2 *3 *4 *4 *3 *4 SEGn *5 COMn *5 VDD V3 V2 VDD+VDDI VDD *8 VDDI *3 *4 *6 CL *6
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Table 11.2 Item Input voltage to primary booster circuit Output voltage from primary booster circuit Primary booster circuit output impedance Reference voltage Voltage adjusting circuit output voltage Secondary boosting output voltage Secondary step-down output voltage
600 500 400
IDD [A]
Symbol VDD2 VOUT Rout VREG V1 V3 MV3
Condition -- Double boosting, no load Double boosting, VDD=2.7V, C=2.2F Ta=25C no load
Standard value Min. Typ. Max. 2.6 5.2 -- 1.16 3.0 8.0 -7.0 -- -- 400 1.20 -- -- -- 3.6 7.2 -- 1.24 5.25 14.0 -4.0
Unit Applicable pin V V V V V V VDD VOUT VOUT *7 V2 V3 MV3
Built-in power supply circuit
Horizontal stripe per 4 dots
300 200 100 0 4 5 6 V2 voltage [V] 7 8 Display RAM all "0"
Condition: VDD = 2.75V, VDDI = 1.8V, frame frequency 180Hz During display, built-in power supply and external oscillation. Typical value when Ta = 25C Fig. 11.1 Dynamic current consumption (During display, liquid crystal drive voltage dependent)
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Rev. 1.0
S1D15G10D08B000
600 500 400
IDD [A]
Horizontal stripe per 4 dots
300 200 100 0 50 100 150 V2 voltage [V] 200 250 Display RAM all "0"
Condition: VDD = 2.75V, VDDI = 1.8V, V2 = 6.0V During display, built-in power supply and built-in oscillation circuit on. Typical value when Ta = 25C Fig. 11.2 Dynamic current consumption (During display, frame frequency dependent)
Table 11.3 Current Consumption in Power Save Mode GND = 0V, VDD = VDDI = 1.8V, VDD = 2.75V and Ta = 25C. Item
Sleep mode
Symbol IDDS
Condition --
Standard value Min. Typ. Max. -- 1.0 10.0
Unit Applicable pin A VDD, VDDI
1600 1400
IDD + IDDI [A]
1200 1000 800 600 400 200 0 0 2 4 6 8 10
data:LOW data:HIGH
Cycle time [MHz]
Condition: VDD = VDDI = 3.0V, built-in power supply and built-in oscillation circuit off . The interface is 8-bit parallel 80 system and the data is 16gray-scale Type A. Typical value when Ta = 25C. Fig. 11.3 Dynamic current consumption (During display RAM access)
Rev. 1.0
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S1D15G10D08B000
Table 11.4 Relation between Oscillated Frequency fOSC, Display Clock Frequency fCL and Frame Frequency of Liquid Crystal Item When built-in oscillation circuit is used When built-in oscillation circuit is not used fCL 43.2kHz (Typ.) *1 External input (fCL) fFR fCL/Dividing ratio 2 x Display duty fCL/Dividing ratio 2 x Display duty
*1: When 180Hz frame frequency device is used. (Display duty : 120, without dividing ratio) fFR represents cycle of framing, not cycle of FR signal. Dividing ratio and display duty are set with the display control command.
DC Characteristics - Supplementary Description *1: Operation is warranted if radical voltage fluctuations occur while MPU is in the process of access. *2: This applies only to RES. *3: D15 to D0 (Input mode) SI, SCL IF1 to IF3, A0, CS, RD (E), WR (R/W), RES, M/S and CLS. *4: D15 to D0 (Input and Output mode) CL, FR SYNC, CA, F1, F2 and DOFF. *5: It represents the resistance value when 0.5V is applied across the output pin SEGn or COMn and respective power terminals (V3, V2, V1, VC, MV1 and MV2). It is specified within the range of the operating voltage (3). RON = 0.5V/I (I is the current conducted when 0.5V is applied across the power supply and output pin). *6: For the relation between oscillated frequency and frame frequency, refer to Table 11.4. The standard value listed in relation to the external input is a recommended value. *7: This is the reference voltage source built into the IC. It is not output to the pin. *8: It indicates the current consumed by the IC alone when the built-in oscillation circuit is in operation and the display is turned on. It does not include current consumed by the LCD panel capacity and wiring capacity. The value is applicable only when access is not being made by MPU.
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EPSON
Rev. 1.0
S1D15G10D08B000 11.2 AC Characteristics
System Bus Read/write characteristics I (80 series MPU)
A0 tAW8 CS *1 WR, RD tCCLW, tCCLR tCCHW, tCCHR tCW8 tAH8
CS *2 tCYC, tCYC2 WR, RD
D0 to D7 (Write) D0 to D7 (Read) tACC8
tDS8
tDH8
tOH8
*1 is when access is made with WR and RD when CS is LOW. *2 is when access is made with CS when WR and RD are LOW.
Signal A0 WR, RD,CS
Symbol tAH8 tAW8 tCYC tCYC2 tCCHW tCCHR tCCLW tCCLR tCW8 tDS8 tDH8 tACC8 tOH8
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse HIGH width (write) Control pulse HIGH width (read) Control pulse LOW width (write) Control pulse LOW width (read) CS-WR, RD time Data setup time Data hold time Read access time Output disable time
Ta=-40 to +85C, VDD=2.6 to 3.6V, VDDI=2.6 to VDD Min. Max. Unit Measuring conditions and others 10 0 190 250 140 70 40 170 45 10 20 -- 5 -- -- -- -- -- -- -- -- -- -- -- 170 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- --
D0 to D7
-- CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum. * All timings must be specified using 30% and 70% of VDD-GND as the reference. * tCCLW and tCCLR are specified by the duration during which CS as well as WR and RD are LOW. * A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
Rev. 1.0
EPSON
47
S1D15G10D08B000
Ta=-40 to +85C, VDD=2.6 to 3.6V, VDDI=1.7 to 2.6V Min. Max. Unit Measuring conditions and others 10 0 190 250 140 70 40 170 40 10 20 -- 5 -- -- -- -- -- -- -- -- -- -- -- 200 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- --
Signal A0 WR, RD,CS
Symbol tAH8 tAW8 tCYC tCYC2 tCCHW tCCHR tCCLW tCCLR tCW8 tDS8 tDH8 tACC8 tOH8
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse HIGH width (write) Control pulse HIGH width (read) Control pulse LOW width (write) Control pulse LOW width (read) CS-WR, RD time Data setup time Data hold time Read access time Output disable time
D0 to D7
-- CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum. * All timings must be specified using 30% and 70% of VDD-GND as the reference. * tCCLW and tCCLR are specified by the duration during which CS as well as WR and RD are LOW. * A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
Signal A0 WR, RD,CS
Symbol tAH8 tAW8 tCYC tCYC2 tCCHW tCCHR tCCLW tCCLR tCW8 tDS8 tDH8 tACC8 tOH8
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse HIGH width (write) Control pulse HIGH width (read) Control pulse LOW width (write) Control pulse LOW width (read) CS-WR, RD time Data setup time Data hold time Read access time Output disable time
Min. 10 0 150 250 110 70 35 170 35 10 20 -- 5
Ta=-40 to +70C, VDD=VDDI=2.9V3% Max. Unit Measuring conditions and others -- -- -- -- -- -- -- -- -- -- -- 200 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- *1
D0 to D7
-- CL=10 to 100pF
*1 tCYC is specified by tCCHW + tCCLW + tr + tf. *2 All timings must be specified using 30% and 70% of VDD-GND as the reference. *3 tCCLW and tCCLR are specified by the duration during which CS as well as WR and RD are LOW. *4 A0 timing is specified by the duration during which CS as well as WR and RD are LOW. *5 Rise and fall time of input signal (tr, tf) must be 15 ns maximum.
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EPSON
Rev. 1.0
S1D15G10D08B000
* Read/write characteristics II (68 series MPU)
A0, R/W
tAW6
CS *1 E
tAH6 tCCHW, tCCHR tCCLW, tCCLR tCW6
CS *2 E
tCYC, tCYC2
D0 to D7 (Write) D0 to D7 (Read)
tDS6 tACC6
tDH6 tOH6
* 1 is when access is made with E when CS is LOW. * 2 is when access is made with CS when E is LOW. Ta =-40 to +85C, VDD=2.6 to 3.6V, VDDI=2.6 to VDD Min. Max. Unit Measuring conditions and others 10 0 190 250 140 70 40 170 40 10 20 -- 5 -- -- -- -- -- -- -- -- -- -- -- 170 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- --
Signal A0, R/W E, CS
Symbol tAH6 tAW6 tCYC tCYC2 tCCLW tCCLR tCCHW tCCHR tCW6 tDS6 tDH6 tACC6 tOH6
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse LOW width (write) Control pulse LOW width (read) Control pulse HIGH width (write) Control pulse HIGH width (read) CS-E time Data setup time Data hold time Read access time Output disable time
D0 to D7
-- CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum. * All timings must be specified using 30% and 70% of VDD-VSS as the reference. * tCCHW and tCCHR are specified by the duration during which CS is LOW and E is HIGH. * A0 and R/W timings are specified by the duration during which CS is LOW and E is HIGH.
Rev. 1.0
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49
S1D15G10D08B000
Ta =-40 to +85C, VDD=2.6 to 3.6V, VDDI=1.7 to 2.6V Min. Max. Unit Measuring conditions and others 10 0 190 280 140 70 40 200 40 10 20 -- 5 -- -- -- -- -- -- -- -- -- -- -- 200 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- --
Signal A0, R/W E, CS
Symbol tAH6 tAW6 tCYC tCYC2 tCCLW tCCLR tCCHW tCCHR tCW6 tDS6 tDH6 tACC6 tOH6
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse LOW width (write) Control pulse LOW width (read) Control pulse HIGH width (write) Control pulse HIGH width (read) CS-E time Data setup time Data hold time Read access time Output disable time
D0 to D7
-- CL=10 to 100pF
* Rise and fall time of input signal (tr, tf) must be 15 ns maximum. * All timings must be specified using 30% and 70% of VDD-VSS as the reference. * tCCHW and tCCHR are specified by the duration during which CS is LOW and E is HIGH. * A0 and R/W timings are specified by the duration during which CS is LOW and E is HIGH.
Signal A0, R/W E, CS
Symbol tAH6 tAW6 tCYC tCYC2 tCCLW tCCLR tCCHW tCCHR tCW6 tDS6 tDH6 tACC6 tOH6
Parameter Address hold time Address setup time Write cycle Read cycle Control pulse LOW width (write) Control pulse LOW width (read) Control pulse HIGH width (write) Control pulse HIGH width (read) CS-E time Data setup time Data hold time Read access time Output disable time
Min. 10 0 150 280 110 70 35 200 35 10 20 -- 5
Ta =-40 to +70C, VDD=VDDI=2.9V3% Max. Unit Measuring conditions and others -- -- -- -- -- -- -- -- -- -- -- 200 60 ns ns ns ns ns ns ns ns ns ns ns ns ns -- *1
D0 to D7
-- CL=10 to 100pF
*1 tCYC is specified by tCCHW + tCCLW + tr + tf. *2 All timings must be specified using 30% and 70% of VDD-VSS as the reference. *3 tCCHW and tCCHR are specified by the duration during which CS is LOW and E is HIGH. *4 A0 and R/W timings are specified by the duration during which CS is LOW and E is HIGH. *5 Rise and fall time of input signal (tr, tf) must be 15 ns maximum.
50
EPSON
Rev. 1.0
S1D15G10D08B000
* Reset timing
VDD RES
tRT1
tRT2
tNNS
Internal control
Normal operation
Signal RES
Symbol tRT1 tRT2 tNNS
Parameter Reset cancel (when the power is turned on.) Reset cancel (during normal operation) Non-Sensitive noize *3
Ta =-40 to +85C, VDD=2.6 to 3.6V, VDDI=1.7 to VDD Min. Max. Unit Measuring conditions and others 350 350 -- -- -- 100 ns ns ns *1
*1 Rise and fall time of input signal (tr, tf) must be 15ns maximum. *2 All timings must be specified using 20% and 80% of VDD-VSS as the reference. *3 Non-Sensitive noise width means that S1D15G10 can usually maintain a state of normal operation, even if the 100ns LOW level noise at maximum mixes into a RES terminal.
Rev. 1.0
EPSON
51
S1D15G10D08B000
* Serial input characteristics
tCSW tCSS
CS
tCSH
tSAS
A0
tSAH
tSCYC tSLW
SCL
tSHW
tf
SI
tSDS
tSDH
tr
Signal CS
Symbol tCSS tCSH tCSW tSAS tSAH tSCYC tSLW tSHW tSDS tSDH
Parameter CS setup time CS hold time CS HIGH width Address setup time Address hold time Clock cycle LOW width HIGH width Data setup time Data hold time
Ta =-40 to +85C, VDD=2.6 to 3.6V, VDDI=1.7 to VDD Min. Max. Unit Measuring conditions and others 10 30 110 90 20 50 15 15 10 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns *1, *2
A0 *3 SCL
SI
* 1: Rise and fall time of every input signal (tr, tf) must be 15 ns maximum. * 2: All timings must be specified using 30% and 70% of VDDI as the reference. * 3: tSAS and tSAH are applicable to the 8-bit serial interface alone.
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EPSON
Rev. 1.0
S1D15G10D08B000
12. MPU INTERFACES (EXAMPLES FOR YOUR REFERENCE)
S1D15G10 series can be directly connected to 80 series and 68 series MPU. Using a serial interface allows you to operate S1D15G10 series with fewer signal lines. In addition to interfaces (1) to (3) given below, using IF1 to IF3 pins enables to employ the 16-bit interface and 9-bit serial interface. When initialization with RES is complete, make sure that input pins of S1D15G00 series are correctly controlled. (1) 80 series MPU - 8-bit interface
VDD VCC A0 A1 to A7 IORQ MPU D0 to D7 RD WR RES GND RESET Decoder A0 CS S1D15G10 VDD
D0 to D7 RD WR RES VSS
IF1 IF2 IF3
VSS
(2) 68 series MPU - 8-bit interface
VDD VCC A0 A1 to A15 VMA MPU D0 to D7 E R/W RES GND RESET VSS Decoder A0 CS S1D15G10 VDD
D0 to D7 E R/W RES VSS
IF1 IF2 IF3
(3) 8-bit serial interface
VDD VCC VDD
A0
A0 CS
A0 to A7 MPU Port1 Port2 RES GND
S1D15G10
Decoder
SI SCL RES VSS RESET
IF1 IF2 IF3
VSS
Rev. 1.0
EPSON
53
S1D15G10D08B000 12.1 Software Setup Examples
12.1.1 When Power is Turned On Input power (VDDI, VDD). Be sure to apply POWER-ON RESET (RES = LOW) Display control (DISCTL) Setting clock dividing ratio and F1/F2 drive selection: Duty setting: Setting reverse rotation number of line: Common scan direction (COMSCN) Setting scan direction: Temperature Gradient Setting (TMPGRD) Oscillation ON (OSCON) Sleep-out (SLIPOUT) Electronic volume control (VOLCTR) Setting volume value : Setting built-in resistance value : Power control (PWRCTR) Setting operation of power supply circuit: Normal rotation of display (DISNOR)/Inversion of display (DISINV): Partial-in (PTLIN)/Partial-out (PTLOUT) Setting fix area: Area scroll set (ASSET) Setting area scroll region: Setting area scroll type: Scroll start set (SCSTART) Setting scroll start address: Data control (DATCTL) Setting normal rotation/inversion of page address: Setting normal rotation/inversion of column address: Setting direction of address scanner: Setting RGB arrangement: Setting gradation: 256-color position set (RGBSET8) Setting color position at 256-color <> 2 dividing, 8 h 1/4 11h reverse rotations COM1 -> COM68, COM69 -> COM132
Oscillation OFF Sleep-in <> 0 0 (3.95) All OFF <> Normal rotation of display Partial-out 0 0 Full-screen scroll 0 <> Normal rotation Normal rotation Column direction RGB 8 gradations All 0
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S1D15G10D08B000
Page address set (PASET) Setting start page address: Setting end page address: Column address set (CASET) Setting start column address: Setting end column address: Memory write command (RAMWR) Writing displayed data : Repeat as many as the number needed and exit by entering other command. Wait until the power supply voltage has stabilized. Enter the power supply control command first, then wait at least 100ms before entering the display ON command when the built-in power supply circuit operates. If you do not wait, an unwanted display may appear on the liquid crystal panel. <> 0 0 0 0 <>
Display ON (DISON):
Display OFF
*1: When the IC is in Sleep In state, the liquid crystal drive power supply and the boosting power output and GND pin are jumpered, therefore, the Sleep Out command must be entered to cancel the Sleep state prior to turning on the built-in circuit. (Note) If changes are unnecessary after resetting, command input is unnecessary.
Rev. 1.0
EPSON
55
S1D15G10D08B000
12.2.2 Command Input Procedure During Power Off *When power-on reset is not used << IC status>> Display off (DISOFF): display is turned off, and all of the common and segment pins become VC potential. Liquid crystal drive power supply circuit off (PWRCTR): built-in power supply circuit stops. Oscillation off (OSCOFF): built-in oscillation circuit stops and all the circuits inside the IC also stop. Sleep In (SLPIN) *2 Stop the power supply (VDDI, VDD). *2: In order to discharge the capacitor connected to the liquid crystal drive power supply circuit, execute the Sleep In command to put the IC in Sleep state prior to stopping the power supply. Stop VDDI and VDD when the output of the liquid crystal drive power supply circuit has dropped sufficiently. *When power-on reset is used Turn on the power-on reset (RES = LOW) *3 Stop the power supply (VDDI, VDD). *3: Stop VDDI and VDD when the output of the liquid crystal drive power supply circuit has dropped sufficiently. (Note:1) This IC is the logic circuit of the VDD-GND and VDDI-GND power supplies, and it controls the liquid crystal output driver. If the VDDI-GND and VDD-GND power supplies are stopped with residual voltage in the liquid crystal drive power supply circuit, the liquid crystal output driver (COM, SEG) may output uncontrolled voltage. Stop VDDI and VDD when the output of the liquid crystal drive power supply circuit has dropped sufficiently. (Note:2) Avoid writing in the display RAM during sleep-in since it may cause too much current to be generated. 12.2.3 Sleep state This IC goes into Sleep state when the Sleep In command and several other commands are executed. When in the Sleep state, IC power consumption will be kept to a minimum. Also, internal status including the display RAM will be maintained, the Sleep Out and several commands will resume the display state. *Setting the Sleep state << IC status>>
1 Display off (DISOFF): display is turned off, and all the common segment and pins become VC potential. 2 Liquid crystal drive power supply circuit off (PWRCTR): built-in power supply circuit stops. 3 Oscillation off (OSCOFF): built-in oscillation circuit stops and all the circuits inside the IC also stop.
Sleep In (SLPIN): commands other than 1 to 3 and display RAM content are maintained. Commands can be entered. (Note) Avoid writing in the display RAM during sleep-in since it may cause too much current to be generated. *Releasing the Sleep state <> Sleep Out (SLPOUT) Oscillation on (OSCON): built-in power supply circuit operates and liquid crystal drive potential is supplied.
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EPSON
Rev. 1.0
S1D15G10D08B000
Wait (approx. 100ms): wait until liquid crystal drive power supply boots and stabilizes. Wait until the power supply voltage stabilizes. Display on (DISON): display comes on and the display RAM content is output. 12.2.4 Refresh Sequence Refreshing of the state setup is recommended by reentering the command, parameters and the display data in order to recover from improper IC operations due to such reasons as noise. Reconfigure the following commands and parameters. Common scan direction (COMSCN) Temperature gradient (TMPGRD) Oscillation on (OSCON) Sleep Out (SLPOUT) Electronic volume control (VOLCTR) Power supply control (PWRCTR) Normal (DISNOR)/Inverted display (DISINV) Partial in (PTLIN)/Partial out (PTLOUT) Area scroll set (ASCSET) Scroll start set (SCSTART) Data control (DATCTL) 256-color position set (RGBSET8) NOP instruction (NOP) *1 Page address set (PASET) Column address set (CASET) Memory write command (RAMWR): display data write Display on (DISON) *1: IC shipment inspection test state can be escaped with NOP instruction. Add this to the refresh sequence. If display control (DISCTL) is reconfigured during display, noise may occur on the display, so omit this from the refresh sequence. Reconfigure with the display off.
Rev. 1.0
EPSON
57
S1D15G10D08B000
13. PERIPHERAL CONNECTION EXAMPLES
13.1 When EEPROM is used
Power voltages: VDDI=1.8 V, VDD=2.7 V Interface: 8-bit parallel interface Primary boosting: Triple Clock: The built-in oscillator circuit is used. V1 voltages: Set by the peripheral EEPROM . PWRCTR: P14= "0" Capacitors: A bypass capacitor is used between VDD and GND pins. A voltage regulator capacitor is used between GND and each of V2, V1, VC and MV1 pins. Connect them by observing the current consumption and voltage waveforms.
S1D15G10D08B100
V3L V2L V1L VCL VCLSL MV1L MV3L VOUT
++
++
+
+ +
1.8V
+
2.7V
Signals to/from S1F17A10
CS A0
D0 to D7
Signals from MPU
RD WR
RES
+ +
TESTA CAP2+ CAP2- CAP1+ CAP1- GND2 GND3 GND VDD3 VDD4 TESTB VDD VDDI FR YSCL F1 F2 DOFF CA SYNC SLP SDA RESET CLOCK TEST1 GND VDDI CL CLS GND VDDI CS A0 GND VDDI SCL SI GND VDDI D0 to D7 GND VDDI D8 to D15 GND VDDI RD WR GND VDDI IF1 IF2 IF3 GND VDDI RES TEST2 M/S VDDI GND GND4 VDD VDD5 VDD2 CAP4+ CAP4- CAP5+ CAP5- MV3R TESTC TESTD MV1R VR VCR V1R V2R V3R
COM132 * * * COM69
SEG1 * * * * * * * * * * * * * * * * * * * * * SEG396
LCD Panel 132 RGB x 132 dots
COM68 * * * COM1
+ +
58
EPSON
Rev. 1.0
S1D15G10D08B000 13.2 When peripheral split resistor is used
Power voltages: VDDI=1.8 V, VDD=2.7 V Interface: 8-bit parallel interface Primary boosting: Triple Clock: The built-in oscillator circuit is used. V1 voltages: Set by external split resistors. PWRCTR: P14= "1" Capacitors: A bypass capacitor is used between VDD and GND pins. A voltage regulator capacitor is used between GND and each of V2, V1, VC and MV1 pins. Connect them by observing the current consumption and voltage waveforms.
S1D15G10D08B100
V3L V2L V1L VCL VCLSL MV1L MV3L VOUT
++
++
+
+ +
+
1.8V 2.7V
CS A0
D0 to D7
Signals from MPU
RD WR
RES
+ +
TESTA CAP2+ CAP2- CAP1+ CAP1- GND2 GND3 GND VDD3 VDD4 TESTB VDD VDDI FR YSCL F1 F2 DOFF CA SYNC SLP SDA RESET CLOCK TEST1 GND VDDI CL CLS GND VDDI CS A0 GND VDDI SCL SI GND VDDI D0 to D7 GND VDDI D8 to D15 GND VDDI RD WR GND VDDI IF1 IF2 IF3 GND VDDI RES TEST2 M/S VDDI GND GND4 VDD VDD5 VDD2 CAP4+ CAP4- CAP5+ CAP5- MV3R TESTC TESTD MV1R VR VCR V1R V2R V3R
COM132 * * * COM69
SEG1 * * * * * * * * * * * * * * * * * * * * * SEG396
LCD Panel 132 RGB x 132 dots
COM68 * * * COM1
+ +
Rev. 1.0
EPSON
59
S1D15G10D08B000
14. EEPROM INTERFACE
The S1D15G10D00B chips provide the Write and Read functions to write the Electronic Control value and built-in resistance ratio into and read them from the peripheral EEPROM (S1F17A10). Using the Write and Read functions, you can store these values appropriate to each LCP panel.
14.1 Conditions when EEPROM read/write is performed
1 The built-in oscillator circuit is already operating. 2 The CL division by 2 and 132 display lines have been set by the Display Control command.
14.2 EEPROM writing instructions
1. 2. 3. 4. Issue the VOLCTR command to set the appropriate Electronic Control value and built-in resistance ratio. Issue the EPCTIN command to select the Control EEPROM mode (for data writing). Issue the EPMWR command to write data into the EEPROM. Issue the EPCTOUT command to cancel the EEPROM Control mode.
14.3 EEPROM data reading instructions
1. Issue the EPCTIN command to select the EEPROM Control mode (for data reading). 2. Issue the EPMRD command to read data from the EEPROM. 3. Issue the EPCTOUT command to cancel the EEPROM Control mode and updates the Electronic Control value and built-in resistance ratio using the read data. Miscellaneous: The MPU can read the Electronic Control value and built-in resistance ratio by issuing a combination of EPSRRD1 or EPSRRD2 and STREAD (Status Read) commands. Notes: As the EPCTIN, EPCWR and EPCRD commands require the following processing times, use a software timer or insert a process to loop the operation by monitoring the status read value of D2 (Access to EEPROM). If these times are insufficient, the Read or Write operation may fail. 1 EPCTIN
5 (sec) fosc / 4 10 (sec) fosc / 320 10 (sec) fosc / 4
2 EPCWR
3 EPCRD
14.4 Connection example
S1D15G10 and S1F17A10 connection example. VDD for both chips is connected to the same potential.
VDD
GND SDA CLOCK RESET
VDD SDA SCK XRST
GND
S1F17A10
S1D15G10D08B100
60
EPSON
Rev. 1.0
S1D15G10D08B000
15. CAUTIONS
Concerning this development specification, users are advised to pay attention to the following precautions. 1. This development specification is subject to modifications without previous notice. 2. This development specification does not grant the industrial property right or any other right, or exercising such rights. Application examples contained in this document are intended only to help users to understand the product better. SEIKO EPSON shall not be liable to any circuit-related problem resulted from using these examples. Users are requested to pay attention to the following points when using S1D15G10 series. Precautions on Light Characteristics of semiconductor devices can be changed when exposed to light as described in the operational principles of solar batteries. Exposing this IC to light, therefore, can potentially lead to its malfunctioning. 1 Care must be exercised in designing the operation system and mounting the IC so that it may not be exposed light during operation 2 Care must be exercised in designing the inspection process and handling the IC so that it may not be exposed to light during the process. 3 The IC must be shielded from light in the front, back and side faces. Precautions on External Noises 1 Internal state of S1D15G10 can be changed when exposed to adversely affecting external factors such as excessive noises though it can maintain the command-instructed operational status and display data. Thus, you must make sure when mounting the IC and designing the operation system that measures for eliminating noises or measures protecting the IC from noises are prepared. 2 In order to be prepared against sudden noise, it is recommended to prepare the software to perform periodic refreshing of operational state (re-setting of commands and re-transfer of display data). Precautions on Mounting COG When mounting COG, you must take into consideration of resistance component generated across the driver chip and externally connected parts (capacitor and resistor) resulting from ITO wiring. This resistance component can interfere with high-speed operation of liquid crystal display or MPU. When mounting COG, you must take into consideration of the following three points in the module design: 1. To minimize resistance between the driver chip pin to the external part. 2. To minimize resistance at the power terminal of the driver chip. 3. To develop sample COG modules with varying degrees of ITO sheet resistance in order to select one with the sheet resistance allowing sufficient operational margins.
Rev. 1.0
EPSON
61

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